The earner of this badge can understand and use SystemVerilog RTL design and synthesis features, including new data types, procedural blocks, statements, operators, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces. They can also appreciate and apply SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and use these features for more effective and efficient verification.

• Type Validation
• Level Intermediate