This badge was issued to Ashok Pulluru on 12 Oct 2023.
- Type Validation
- Level Intermediate
Verilog Language and Application v26.0 Exam
Issued by
Cadence Design Systems
The earner of this badge can use fundamental Verilog constructs to create simple designs. He can ensure that Verilog designs meet the requirements for synthesis and he can also develop Verilog test environments of significant capability and complexity.
- Type Validation
- Level Intermediate
Earning Criteria
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Score 96% or greater on the exam.