This badge was issued to Raghav Marwah on 25 Jul 2023.
- Type Validation
- Level Intermediate
SystemVerilog Accelerated Verification with UVM v1.2.5 Exam
Issued by
Cadence Design Systems
The earner of this badge can create UVM Verification Components (UVCs) . They can configure, customize and connect UVCs in a UVM verification environmment. They can create UVC and system-level sequences to drive stimulus patterns into a DUT. They can implement and integrate scoreboards. They also have a basic knowledge of UVM Register Modelling. Badge earners understand industry best-practices for creating UVCs and UVM verification environments.
- Type Validation
- Level Intermediate
Earning Criteria
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Score 96% or greater on the exam.