The earner of this badge can use SystemVerilog object-oriented features for verification. They can declare and use class instances with static and dynamic members. They can use inheritance, polymorphism, casting, virtual methods and classes. They can create, manipulate aggregate and composite class hierarchies with reference, shallow and deep operations. They can use constrained randomization in class hierarchies. They can define a Verification Component, connect to a DUT using virtual interface

• Type Validation
• Level Intermediate