The earner of this badge can understand the advantages of Assertion-Based Verification (ABV) using SystemVerilog Assertions (SVA). They can demonstrate the full range of language features. They understand good and bad SVA coding styles and design techniques. They can utilize a methodology for SVA property reuse and describe behaviors that SVA cannot describe and how to overcome these issues. They can also explain what is Formal Analysis, what it does, how it works and run basic proofs.

• Type Validation
• Level Intermediate