The earner of this badge can understand and use the SystemVerilog RTL design and synthesis features, including new data types, procedural blocks, operators, enhancements to tasks and functions, hierarchy and connectivity features, and interfaces. He can appreciate and apply the SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for effective and efficient verification.

• Type Validation
• Level Intermediate