ESD Design Engineer Certification (EDEC)
  • Type Certification
  • Level Intermediate
Additional Details

ESD Design Engineer Certification (EDEC)

Issued by EOS/ESD Association, Inc

This certification provides courses that give the foundation for ESD Design Engineers. Courses cover integrated circuit ESD, protection designs, testing essentials, troubleshooting, failure analysis, and TLP fundamentals. The certification is comprised of eight online courses and a knowledge assessment test.

  • Type Certification
  • Level Intermediate
Additional Details

Skills

Earning Criteria

  • DD103: AN OVERVIEW OF INTEGRATED CIRCUIT ESD: This three hour tutorial is focused on integrated circuit ESD fundamentals, and is targeted for two audiences: the IC circuit designer who needs knowledge of how ESD can affect IC design, test, handling and system use; and those engineers wishing to be introduced to IC ESD, as a primer to further study.
  • DD110: ESD FROM BASICS TO ADVANCED PROTECTION DESIGNThis course gives a comprehensive overview from ESD basics to ESD on-chip design principles, covering up to the latest silicon technologies appealing to a variety of engineers from design to process technology, and failure analysis to quality
  • DT100: HBM TESTING ESSENTIALSThis tutorial addresses the details of human body model (HBM) qualification testing
  • DT200: CDM TESTING ESSENTIALSThis tutorial will give students the fundamental information required to quickly learn the CDM testing method on commercial CDM test equipment and the associated oscilloscope/metrology chain information needed to capture and interpret CDM waveforms.
  • DT201: LATCH-UP TESTING AND TROUBLESHOOTINGThis tutorial focuses on latch-up testing and troubleshooting. Latch-up is a failure mechanism primarily seen in CMOS and BiCMOS technologies but can be present in bipolar technologies. During process development, resistance to latch-up is generally characterized and design rules are implemented at device circuit block layout.
  • DT142: FUNDAMENTALS OF FAILURE ANALYSISFailure analysis is the diagnostic tool of the semiconductor industry. It is the semiconductor equivalent of forensic science. Failure analysis unravels the mystery behind how and why a part failed, determining the root cause and corrective actions needed to prevent future failures.
  • DT210: TLP FUNDAMENTALS – UNDERSTANDING THE EQUIPMENT OPTIONS AND IV DATAThis tutorial explains what transmission line pulsing (TLP) is and how it can be used for ESD design and development. Taking accurate TLP measurements is important; thus, how TLP systems make measurements and produce IV plots will be reviewed.
  • DD134: FUNDAMENTALS OF ESD SYSTEM LEVELThis tutorial is intended to help those tasked with designing and testing prod-ucts to system-level ESD standards by providing first an overview of what the real-world system ESD threats are and the associated standards that describe these events. Then detailed information on qualification testing is given on IEC 61000-4-2, the most widely used standard, but also ISO 10605 and other standards.