Those with the Timing Closure for Intel® FPGAs Course Completion badge have learned the best practices for closing timing on an FPGA design in the Intel Quartus Prime Pro software, can analyze timing reports generated by Timing Analyzer as a starting point for timing closure, know the tools available in Intel Quartus Prime Pro to help in meeting timing, know how to choose settings/assignments to get the best performance, identify the most common types of timing failures and how to solve them.