Earners of this badge are able to use UVM to verify complex digital designs at block & chip level, identifying contained bugs, and closing functional coverage. They can explain use of sequence items, sequences, and sequencers for creating test scenario stimulus. Earners can leverage UVM Factory for creation and substitution of class objects and components while using UVM configuration database to share resources between objects and component hierarchy without reducing simulation performance.

• Type Learning
• Level Advanced
• Time Months