Questa Verification IP - v22.18

Issued by Siemens Software

Earners of this badge have successfully completed the 25 question exam to show basic knowledge of how to create stimulus and check results for standard protocols with Questa Verification IP and how to integrate QVIP in a UVM testbench.

Type Certification
Level Foundational
Time Hours
Cost Free

Additional Details

Skills

Electronic Design Automation (EDA) Software
Electronics Systems Design
Functional Verification
IC Logic Verification
SystemVerilog
UVM

Earning Criteria

Complete a 90-minute exam of 50 questions and achieve a 90% or higher score to earn this badge.

Standards

UVM

The UVM standard improves interoperability and reduces the cost of repurchasing and rewriting IP for each new project or electronic design automation tool. It also makes it easier to reuse verification components.