- Type Learning
- Time Hours
System Verilog for Verification Seminar
Issued by
Siemens Software
Earners of this badge are able to identify best practices collected over the years in building flexible and advanced Verification IPs. They also are familiar with some of the major challenges and the solutions applied to meet industry requirements for functional verification.
- Type Learning
- Time Hours
Earning Criteria
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Attended 100% of seminar including Q&A sessions.