SystemVerilog UVM - v22.18

Issued by Siemens Software

Earners of this badge have successfully completed the 50 question exam to show basic knowledge of UVM (Universal Verification Methodology) for creating basic UVM testbenches and UVM stimulus.

Type Certification
Level Foundational
Time Hours
Cost Free

Additional Details

Skills

Earning Criteria

Complete 90 minute exam of 50 questions and achieve 80% or higher score to earn the badge.
If you don't have an active subscription to the Badging Library CLICK HERE and use "Certnow" discount code to subscribe for FREE and earn a Siemens Verified Digital Badge
If you have an active subscription, click HERE to access the exam.
You must log in/create a Siemens Support Center account to be able to take the exam. for more information please contact us at xceleratoracademy_eda.disw@siemens.com

Standards

UVM

The UVM standard improves interoperability and reduces the cost of repurchasing and rewriting IP for each new project or electronic design automation tool. It also makes it easier to reuse verification components.