Earners of this badge are able to design HDL code for combinational circuits and sequential circuits using Questasim and analyze MOS and CMOS transistor characteristics using Tanner and Calibre. They also can illustrate the fabrication processes of CMOS & logic families and make architectural choices and performance tradeoffs involved in designing using Tanner and Oasys. Earners can identify the different FPGA architectures and testability of VLSI circuits using Tessent.

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