VLSI Verification Methodologies Course- Vellore Institute of Technology, Vellore

Issued by Siemens Software

Earners of this badge are able to develop test plans, build testbench in System Verilog and perform functional simulations in Questasim. They are able to work with the specifications to perform randomizations, assertions and ensure functional and code coverage of the RTL. Earners are also can create reusable verification environment using UVM.

Type Learning
Time Months

Skills

Debuggin
QuestaSim
Simulation
System Verilog
Test Planning
UVM
Verification

Earning Criteria

Pass the course with B grade or higher.
Completed the project to verify a design using SV/UVM.
Professor approved portfolio submitted on or before due date.