The earner of this badge demonstrated the knowledge required for running Synopsys Design Compiler® NXT in Topographical mode to perform all the steps in the RTL synthesis flow. This includes synthesizing a block-level RTL design, analyzing the synthesis results for timing and congestion, generating a final gate-level netlist with acceptable postplacement timing and congestion, and verifying the logic equivalence of the synthesis transformations with the RTL design using Synopsys Formality® tool.

• Type Validation
• Level Foundational