The earner of this badge has demonstrated the knowledge required for completing key block-level floorplanning steps using the Synopsys Fusion Compiler™ tool. This includes executing clock tree synthesis (CTS) or the concurrent clock-and-data (CCD) flow, analyzing the clock tree, running post-CTS global route-based optimization, specifying timing and DRC constraints, performing routing setup and routing, and optimizing the post-route design.

• Type Validation
• Level Foundational