The earner of this badge has demonstrated the knowledge required for creating chip and block-level floorplans using hierarchical(top-down) design planning approach using the Synopsys Fusion Compiler™ tool. This includes SOC designs with multi-voltage (UPF) with multiple levels of physical hierarchy which can contain a mix of multiply-instantiated blocks (MIBs), black boxes, and partial netlists.

• Type Certification
• Level Foundational