The earner of this badge demonstrated the knowledge required for running a complete place and route flow on block-level designs using the Synopsys IC Compiler™ II tool. This includes GUI usage for analyzing the layout during the various design phases, creating NDM reference libraries, creating block-level floorplans, performing concurrent MCMM standard cell placement and related optimizations, and generating the output files for signoff extraction and static timing analysis.

• Type Validation
• Level Foundational