Learn all about Physical Design fundamentals in RTL to GDS II flow - modeling abstraction, timing, signal integrity, low power, UPF, DFT, library preparation, library creation and setting constraints. Get hands on experience with Synopsys Fusion Compiler™ for design creation, synthesis and implementation. Learn to read and manage RTL, apply power intent, floorplanning, configure CCD & power optimization, improve timing and congestion, execute clock tree synthesis, and route-based optimization.

• Type Validation
• Level Foundational
• Time Weeks
• Cost Paid