The earner of this badge has demonstrated the knowledge required to develop SystemVerilog testbenches using UVM base classes. This includes creating the UVM environment to build and manage random stimulus and sequences, drivers, monitors, scoreboards, and functional coverage objects, implement a collection of test cases each targeting a corner case of interest and create an abstraction of design-under-test (DUT) registers and managing these registers during tests.

• Type Validation
• Level Foundational