This exam enables you to demonstrate the knowledge required for using Synopsys TestMAX™ DFT to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. This also includes techniques to support large, multimillion gate SoC designs including the bottom-up scan insertion flow in the logical (Design Compiler®) domain, inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks, using DFTMAX™.

• Type Certification
• Level Foundational